Integrating Arm Cortex-M soft CPU IP into FPGAs
If you ever wanted to get started with FPGAs without becoming a hardware expert, or already are a hardware expert who wants to integrate Arm Cortex-M soft CPU IP into their FPGA designs, this workshop is for you.
In this half-day virtual workshop you will get hands-on experience with creating, programming, debugging, and developing applications for Arm Cortex-M in Xilinx FPGAs, through DesignStart FPGA.
NO FPGA EXPERIENCE is required to get started!
August 14, 2019
For more information about DesignStart FPGA, visit arm.com/resources/designstart/designstart-fpga
Duration: 4 Hours
Get access to experts from Arm, Xilinx and Digilent
Three Hands-on Labs
Live Q&A Session
Kick-Off and Workshop Overview
What is DesignStart FPGA and How to Access Arm Cortex-M soft CPU IP for Free
Design Start FPGA and Use Cases for Cortex-M1 and Cortex-M3 Processors
Key Interfaces of Cortex-M1 and Cortex-M3 Processors
Software Development Flow / Tool Chain
Lab #1 Exploring the Architecture in Xilinx Vivado Design Tools
Lab #2 Saying Hello World
Lab #3 Completing A Simple Robot / Motor Control Application
Register for the workshop and receive a coupon for 15% off all required hardware.
*Must be the S7-50T version.
Attendees will receive detailed software download requirements and instructions prior to the workshop. All downloads are free of charge.
Director, Adiuvo Engineering and Training
Adam Taylor is an expert in design and development of embedded systems and FPGAs for several end applications. Throughout his career, Adam has used FPGAs to implement a wide variety of solutions from RADAR to safety critical control systems, with interesting stops in image processing and cryptography along the way.
Ecosystem Manager, Arm
Alessandro is the ecosystem manager in the automotive and IoT division at Arm. Alessandro is part of a global team that focuses on driving innovation by supporting a diverse range of developers building solutions in IoT, embedded, robotics, drones, machine learning and security. Before moving to this role, Alessandro has worked as a design and validation engineer on many different Arm products, some of which are in a variety of devices you use every day.
Product Line Manager, Xilinx
Jayson is the Product Line Manager for Xilinx’s Cost-Optimized Portfolio, which includes Spartan, Artix, and Zynq-7000 devices, and the Zynq UltraScale+ MPSoC family. With over 20 years of Xilinx design, technical support, training, and marketing experience, Jayson leads the design of multiple evaluation boards, such as the Spartan-6LX9 Microboard, Zedboard, and MicroZed.